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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
Serial Input Communication
?
Table 8. SI Message Bit Assignment
SPI communication compliant to 3.3 and 5.0 V is
accomplished using 16-bit messages. A message is
transmitted by the master starting with the MSB, D15, and
Bit Sig
MSB
SI Msg Bit
D15 : D11
Message Bit Description
Register address bits.
ending with the LSB, D0. Each incoming command message
on the SI pin can be interpreted using the bit assignment
described in Table 8 . The 5 bits D15 : D11, called register
address bits, are used to select the command register. Bit
D10 is the watchdog bit. The remaining 10 bits, D9 : D0, are
used to configure and control the output and its protection
LSB
D10
D9 : D0
Watchdog in: toggled to satisfy watchdog
requirements.
Used to configure inputs, outputs, device
protection features, and SO status content.
features. Multiple messages can be transmitted in
succession to accommodate those applications where daisy
chaining is desirable or to confirm transmitted data as long as
the messages are all multiples of 16 bits. Any attempt made
to latch in a message that is not 16 bits will be ignored.
All SPI registers are reset (all bits equal 0) in case of RST
equals 0 or fail mode (Fail=1).
Table 9. Serial Input Address and Configuration Bit Map
SI Address
Device Register Addressing
The register addresses (D15 : D11) and the impact of the
serial input registers on device operation are described in this
section. Table 9 summarizes the content of the SI registers.
SI Data
SI Register D1 D1 D1 D1 D1
5 4 3 2 1
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Initializatio
n
0
0
0
0
0
WD
0
0
STOPen
PWM
sync
0
MUX2
MUX1
MUX0
SOA1
SOA0
Config OL
0
0
0
0
1
WD
LED LED
Control5 Control4
LED
Control3
LED
Control
2
LED
Control OLLED5 OLLED4 OLLED3 OLLED2 OLLED1
1
Config
Prescaler
Config SR
Config
CSNS
Control
OUT1
Control
OUT2
Control
OUT3
Control
OUT4
Control
OUT5
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
1
1
0
1
0
1
WD
WD
WD
WD
WD
WD
WD
WD
0
1
CSNS
sync
Phase2
Phase2
Phase2
Phase2
Phase2
PR1
SR1
0
Phase1
Phase1
Phase1
Phase1
Phase1
PR2
SR2
0
ONoff
ONoff
ONoff
ONoff
ONoff
PR3
SR3
0
PWM6
PWM6
PWM6
PWM6
PWM6
0
0
0
PWM5
PWM5
PWM5
PWM5
PWM5
0
0
NO_OC
HI5
PWM4
PWM4
PWM4
PWM4
PWM4
0
0
NO_OC
HI4
PWM3
PWM3
PWM3
PWM3
PWM3
PR4
SR4
NO_OC
HI3
PWM2
PWM2
PWM2
PWM2
PWM2
PR5
SR5
NO_OC
HI2
PWM1
PWM1
PWM1
PWM1
PWM1
PR6
0
NO_OC
HI1
PWM0
PWM0
PWM0
PWM0
PWM0
Control
External
0
1
1
1
0
WD
Phase2
Phase1
ONoff
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
Switch
35XS3500
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
27
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